The subject invention is generally directed to scan flip-flop cells, and is directed more particularly to a scan flip-flop cell that includes a feedback path by which the data output of the flip-flop cell can be held for an arbitrary amount of time, and a latch in the feedback path allowing the cell to store two bits of test data simultaneously.
Very large scale integrated circuits (VLSI circuits) often employ special circuits to aid testability so as to make the operation of testing the VLSI simpler, more efficient and more effective.
A very common built-in test circuit is the scan path or chain by which the bistable elements (flip-flops and/or latches) within a VLSI circuit are connected into a shift register called a scan path or scan chain. With the VLSI in test mode, it is possible to shift an arbitrary pattern into the bistable elements. The VLSI circuit is then operated in the normal mode for one clock period, which causes the bistable element contents to act as inputs to the internal combinational logic, and causes subsequent responses values to be stored in the bistable elements. The VLSI is again placed into test mode to allow the contents of the bistable elements to be shifted out and compared with the correct response.
While current scan path testing is effective, there are considerations with known scan circuitry including the inability to perform path delay testing (also called AC testing). Path delay testing requires that the input to combinational logic must transition from one predefined pattern (the precursor pattern) to another predefined pattern (the driving pattern). The response from the combinational logic is sampled via the bistable elements after the proper propagation time. Both precursor and driving patterns are necessary to assure that a particular path-under-test actually changes state in the manner desired. Scan path testing cannot provide two arbitrary test patterns within one clock, since the second pattern must be scanned-in with multiple clocks, and the first pattern cannot be retained until the second arrives. Several methods have been employed or proposed which would allow scan path testing to provide two successive, arbitrary test patterns within one clock time period. These have been complex, requiring multiple clocks, or very large in use of available area, or costly in terms of having more internal delay.
Another consideration of known scan circuitry is the inability to intermix in-system verification testing, which is performed to check that the VLSI circuits are not defective, with normal system operations, since scanning test patterns into the bistable elements would necessarily erase the operational data stored therein.